Determination of the Sensitive Volume and Critical Charge for Induction of SEU in Nanometer SRAMs

Raisali, Gholamreza; Soleimaninia, Masume; Moslehi, Amir

doi:10.30699/jsst.2023.1423

Document Type : Research Paper

Authors

¹ Professor, Nuclear Science and Technology Institute, Atomic Energy Organization of Iran, Tehran, Iran

² Ph.D., Nuclear science and technology research institute, Technical expert/atomic energy organization of Iran, Tehran, Iran

³ Assistant Professor, Nuclear science and technology research institute, Atomic Organization of Iran, Tehran, Iran

https://doi.org/10.30699/jsst.2023.1423

Abstract

In this paper, the sensitive volume and critical charge of a 65-nm CMOS SRAM as two important quantities in Single Event Upset (SEU) calculations have been determined. SEU is the most common event in space investigations. To this purpose, a memory cell which is consisted of NMOS and PMOS was simulated using Silvaco TCAD tool. Then, the variations in output voltages were studied after striking incident particles with different values of Linear Energy Transfer (LET) at different regions of the transistors. The Qcritical was obtained by integrating the output current when the output voltages were inverted. To determine the sensitive volume, the minimum amount of LET in which the output logic state of the memory cell flips, was considered as a criteria of sensitivity. The results showed the value of 0.054 µm3 and 1.48 fC for sensitive volume and critical charge, respectively which are in good agreement with the references.

Keywords

Main Subjects

investigating space radiation

References

[1] G. Hubert, L. Artola, and D. Regis, “Impact of scaling on the soft error sensitivity of bulk, FDSOI and FinFET technologies due to atmospheric radiation,” Integration, vol. 50, pp. 39-47, 2015.

[2] P.E. Dodd, and L.W. Massengill, “Basic mechanisms and modeling of single-event upset in digital microelectronics.”, IEEE Transactions on nuclear Science Vol.50, No. 3 , pp 583-602, 2003.

[3] C. Slayman, “Soft error trends and mitigation techniques in memory devices,” In 2011 Proceedings-Annual Reliability and Maintainability Symposium., pp. 1-5, IEEE 2011.

[4] F. Wang, and D.V. Agrawal, “Single event upset: An embedded tutorial,” In 21st International Conference on VLSI Design, pp. 429-434. IEEE, 2008.

[5] D. F. Heidel, P. k. Rodbell, P. Oldiges, and et al. “Single-event-upset critical charge measurements and modeling of 65 nm silicon-on-insulator latches and memory cells,”IEEE Trans on nuclear science , Vol.53, No. 6, pp. 3512-3517, 2006.

[6] M. Zerarka, P. Austin, and M. Bafleur. “Comparative study of sensitive volume and triggering criteria of SEB in 600 V planar and trench IGBTs.” Microelectronics Reliability, Vol. 51, No. 9-11, pp 1990-1994, 2011.

[7]M. Zerarka , P. Austin, F. Morancho, and et al. “Analysis study of sensitive volume and triggering criteria of single‐event burnout in super‐junction metal‐oxide semiconductor field‐effect transistors.” IET Circuits, Devices & Systems ,Vol. 8, No. 3 , pp 197-204, 2014.

[8]M. Zerarka , P. Austin , A. Bensoussan, and. Et al. “TCAD simulation of the single event effects in normally-OFF GaN transistors after heavy ion radiation.” IEEE Transactions on Nuclear Science , Vol. 64, No. 8 , pp 2242-2249, 2017.

[9] R. Naseer , Y. Boulghassoul, J. Draper, and et al. “Critical charge characterization for soft error rate modeling in 90nm SRAM.” In 2007 IEEE International Symposium on Circuits and Systems, pp. 1879-1882. IEEE, 2007.

[10] E. Farjallah, V. Gherman, J-M. Armani, and L. Dilillo. “Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells.” In 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), pp. 1-5. IEEE, 2018.

[11] R. Rajaei, B. Asgari, M.Tabandeh, and M. Fazeli. “Design of robust SRAM cells against single-event multiple effects for nanometer technologies.” IEEE Transactions on Device and Materials Reliability , Vol.15, No. 3 , pp.429-436 , 2015.

[12] Victory Device User’s Manual, Silvaco, Inc. 4701 Patrick Henry Drive, Bldg. 2 Santa Clara, CA 95054, (408) 567-1000, http://www.silvaco.com, January 26, 2015.

[13] M. Sajid, N. G. Chechenin, F. S. Torres, and, et al., “Single Event Upset rate determination for 65 nm SRAM bit-cell in LEO radiation environments,” Microelectronics Reliability, Vol. 78, pp. 11-16, 2017.

[14] P. KUMAR, M. Vashishath, P.K. bANSAL. “An Investigation into NMOS at 65 nm using Silvaco TCAD,” International Journal of Management, Technology and Engineering, Vol. 8, 2018.

[15] B. Hoefflinger, “ITRS: The international technology roadmap for semiconductors.” In Chips 2020: a guide to the future of nanoelectronics pp. 161-174. Springer, Berlin, Heidelberg, 2011.

[16] I. Kumar, A. Bharth, A. K. Jaiswal, A. Kumar. “Optimization of Threshold Voltage for 65nm PMOS Transistor Using Silvaco TCAD Tools.” IOSR Journal of Electrical and Electronics Engineering , Vol. 6, No. 1, pp. 62-67, 2013.

[17] J. D. Black, D. R. Ball Ii, W. H. Robinson, and et al. “Characterizing SRAM single event upset in terms of single and multiple node charge collection.” IEEE Transactions on Nuclear Science , Vol. 55, No. 6, pp 2943-2947, 2008.

[18] H. Dussault, J. W. Howard, R. C. Block, M. R. Pinto, and et al. “Numerical simulation of heavy ion charge generation and collection dynamics.” IEEE transactions on nuclear science , Vol. 40, No. 6 , pp. 1926-1934, 1993.

[19] K. M. Warren, R. A. Weller, M. H. Mendenhall, and et al, "The contribution of nuclear reactions to heavy ion single event upset cross-section measurements in a high-density SEU hardened SRAM." IEEE transactions on nuclear science , Vol. 52, No. 6, pp. 2125-2131, 2005.

[20] B. Ye, J. Liu, T.S Wang, and et al “Impact of energy straggle on proton-induced single event upset test in a 65-nm SRAM cell.” Chinese Physics B , Vol. 26, No. 8, p. 088501, 2017.

[21] M. Soleimaninia, G. Raisali, and A. Moslehi. “A detailed simulation study on the effect of energy and angle of incidence for low energy protons on Single Event Upsets induced in nanometer CMOS SRAM.” Journal of Instrumentation , Vol. 16, No. 03: p. 03015, 2021.

[22] M. Manzar, S. Hafiz, S. Khan, and et al , “Intensity Threshold Study of 6T 7T and 10T SRAM by TCAD Simulation with Optical Beam.” In International Conference on Solid State Science and Technology. ICSSST, Vol. 24, No 1, pp 210-219, 2016.

Space Science and Technology

Determination of the Sensitive Volume and Critical Charge for Induction of SEU in Nanometer SRAMs

References

References

Volume 16, Issue 2 - Serial Number 56
June 2023
Pages 43-54

Determination of the Sensitive Volume and Critical Charge for Induction of SEU in Nanometer SRAMs

References

References

Volume 16, Issue 2 - Serial Number 56June 2023Pages 43-54

Volume 16, Issue 2 - Serial Number 56
June 2023
Pages 43-54